7035L
Features
- True Dual-Ported memory cells which allow simultaneous reads of the same memory location
- High-speed access
- mercial: 15ns (max.)
- Low-power operation
- IDT7035L Active: 800m W (typ.) Standby: 1m W (typ.)
- Separate upper-byte and lower-byte control for multiplexed bus patibility
- IDT7035 easily expands data bus width to 36 bits or more using the Master/Slave select when cascading more than one device
- M/S = H for BUSY output flag on Master M/S = L for BUSY input on Slave
- Interrupt Flag
- On-chip port arbitration logic
- Full on-chip hardware support of semaphore signaling between ports
- Fully asynchronous operation from either port
- Battery backup operation- 2V data retention
- TTL-patible, single 5V (±10%) power supply
- Available in 100-pin Thin Quad Flatpack
Functional Block Diagram
R/WL UBL
R/WR UBR
LBL CEL OEL
I/O9L-I/O17L
I/O0L-I/O8L BUSYL(1,2)
I/O Control
I/O Control
A12L A0L
Address Decoder
CEL OEL R/WL
MEMORY ARRAY
ARBITRATION INTERRUPT...
