82P33731 Overview
10GBASE-R, 10GBASE-W, 40GBASE-R and 100GBASE-R APLL1 and APLL2 generate clocks with jitter < 1 ps RMS (12 kHz to 20 MHz) for: 1000BASE-T and 1000BASE-X Fractional-N input dividers support a wide range of reference frequencies Locks to 1 Pulse Per Second (PPS) references DPLLs, APLL1 and APLL2 can be configured from an external EEPROM after reset.
82P33731 Key Features
- posite clock inputs (IN1 and IN2) accept 64 kHz synchronization interface signals per ITU-T G.703
- Differential reference inputs (IN3 to IN8) accept clock frequencies between 1 PPS and 650 MHz
- Single ended inputs (IN9 to IN14) accept reference clock frequencies between 1 PPS and 162.5 MHz
- Loss of Signal (LOS) pins (LOS0 to LOS3) can be assigned to any clock reference input
- Reference monitors qualify/disqualify references depending on activity, frequency and LOS pins
- Automatic reference selection state machines select the active reference for each DPLL based on the reference monitors,
- Fractional-N input dividers enable the DPLLs to lock to a wide range of reference clock frequencies including: 10/100/10
- Any reference inputs (IN3 to IN14) can be designated as external sync pulse inputs (1 PPS, 2 kHz, 4 kHz or 8 kHz) associ
- FRSYNC_8K_1PPS and MFRSYNC_2K_1PPS output sync pulses that are aligned with the selected external input sync pulse input
- DPLL1 can be configured with bandwidths between 0.09 mHz and 567 Hz
82P33731 Applications
- APLL3 is Voltage Controlled Crystal Oscillator (VCXO) based and generates clocks with jitter <0.3 ps RMS (10 kHz to 20 MHz) for: 10GBASE-R, 10GBASE-W, 40GBASE-R
- APLL1 and APLL2 generate clocks with jitter < 1 ps RMS (12 kHz to 20 MHz) for: 1000BASE-T and 1000BASE-X
