82P33741 Datasheet PDF - Renesas Port Synchronizer Specs

82P33741 - Port Synchronizer

Datasheet Summary

Description

The 82P33741 Port Synchronizer for IEEE 1588 and 10G/40G Synchronous Ethernet provides tools to manage timing references, clock conversion and timing paths for IEEE 1588 and Synchronous Ethernet (SyncE).

Features

Differential reference inputs (IN1 to IN6) accept clock frequencies between 2 kHz and 650 MHz.
Single ended inputs (IN7 to IN12) accept reference clock frequencies between 2 kHz and 162.5 MHz.
Loss of Signal (LOS) pins (LOS0 to LOS3) can be assigned to any clock reference input.
Reference monitors qualify/disqualify references depending on activity, frequency and LOS pins.
Automatic reference selection state machines select the active reference for e.

Datasheet Details

Part number	82P33741
Manufacturer	Renesas
File Size	0.97 MB
Description	Port Synchronizer
Datasheet	82P33741 Datasheet
Additional preview pages of the 82P33741 datasheet.

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Full PDF Text Transcription

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Port Synchronizer for IEEE 1588 and 10G/ 40G/ 100G Synchronous Ethernet 82P33741 Datasheet HIGHLIGHTS • DPLL1 and DPLL2 can be used on line cards to manage the generation of synchronous port clocks and IEEE 1588 synchronization signals based on multiple system backplane references • DPLL3 can be used on line cards to select incoming line clocks for use on system backplanes; it can also be used for general purpose timing applications • APLL1 and APLL2 generate clocks with jitter < 1 ps RMS (12 kHz to 20 MHz) for: 1000BASE-T and 1000BASE-X ports and to generate IEEE 1588 time stamp clocks and 1 pulse per second (PPS) signals • APLL3 is Voltage Controlled Crystal Oscillator (VCXO) based and generates clocks with jitter <0.

Published: Aug 13, 2020 |