Renesas Electronics 82P33831
Synchronization Management
| Part No. | 82P33831 |
|---|---|
| Datasheet | 82P33831 Download |
| Manufacturer |  Renesas Electronics |
| Description | Synchronization Management |
| Buy | Stock & Price |
FEATURES
● Composite clock inputs (IN1 and IN2) accept 64 kHz synchronization interface signals per ITU-T G.703● Differential reference inputs (IN3 to IN8) accept clock frequencies between 1 PPS and 650 MHz
● Single ended inputs (IN9 to IN14) accept reference clock frequencies between 1 PPS and 162.5 MHz
● Loss of Signal (LOS) pins (LOS0 to LOS3) can be assigned to any clock reference input
● Reference monitors qualify/disqualify references depending on activity, frequency and LOS pins
● Automatic reference selection state machines select the active reference for each DPLL based on the reference monitors, priority tables, revertive and non-revertive settings and other programmable settings
● Fractional-N input dividers enable the DPLLs to lock to a wide range of reference clock frequencies including: 10/100/1000 Ethernet, 10G/40G/100G Ethernet, OTN, SONET/SDH, PDH, TDM, GSM, CPRI and GNSS frequencies
● Any reference input (IN3 to IN14) can be designated as external sync pulse inputs (...
