82V3399 - Clock Generatiion

Datasheet Summary

Description

The 82V3399 is an integrated, single-chip solution for the Synchronous Equipment Timing Source for Stratum 3, 4E, 4, SMC, EECOption1, EEC-Option2 clocks in SONET / SDH / Synchronous Ethernet equipment, DWDM and Wireless base station.

Features

s 0.5 mHz to 560 Hz bandwidth.
Provides node clock for ITU-T G.8261/G.8262 Synchronous Ethernet (SyncE).
Exceeds GR-253-CORE (OC-192) and ITU-T G.813 (STM-64) jitter generation requirements.
Provides node clocks for Cellular and WLL base-station (GSM and 3G networks).
Provides clocks for DSL access concentrators (DSLAM), especially for Japan TCM-ISDN network timing based ADSL equipments.
Provides clocks for 1 Gigabit and 10 Gigabit Ethernet applicatio.

Renesas

📥 Download Datasheet

Datasheet Details

Part number	82V3399
Manufacturer	Renesas
File Size	211.40 KB
Description	Clock Generatiion
Datasheet	82V3399 Datasheet
Additional preview pages of the 82V3399 datasheet.

📁 Similar Datasheet

Other Datasheets by Renesas

82V3001A - WAN PLL

Full PDF Text Transcription

Click to expand full text

Synchronization Management WAN PLL and Clock Generatiion for IEEE-1588 82V3399 SHORT FORM DATA SHEET This short form datasheet is intended to provide an overview only. Additional details are available from IDT. Contact information may be found on the last page. FEATURES HIGHLIGHTS • Single chip PLL: • Features 0.5 mHz to 560 Hz bandwidth • Provides node clock for ITU-T G.8261/G.8262 Synchronous Ethernet (SyncE) • Exceeds GR-253-CORE (OC-192) and ITU-T G.

Published: Aug 13, 2020 |