8413S12B Description
The 8413S12B is a PLL-based clock generator. This high performance device is optimized to generate the processor core reference clock, the PCI-Express, sRIO, XAUI, SerDes reference clocks and the clocks for both the Gigabit Ethernet MAC and PHY. The clock generator offers ultra low-jitter, low-skew clock outputs.
8413S12B Key Features
- Ten selectable 100MHz, 125MHz, 156.25MHz and 312.5MHz
- One single-ended QG LVCMOS/LVTTL clock output at 125MHz
- One single-ended QF LVCMOS/LVTTL clock output at 50MHz
- Two single-ended QREFx LVCMOS/LVTTL outputs at 25MHz
- Selectable external crystal or differential (single-ended) input
- Crystal oscillator interface designed for 25MHz, parallel resonant
- Differential CLK, nCLK input pair that can accept: LVPECL, LVDS
- Internal resistor bias on nCLK pin allows the user to drive CLK
- Supply Modes, (125MHz QG output and 25MHz QREFx outputs)
- Supply Modes, (HCSL outputs, and 50MHz QF output)