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85105I - Differential/LVCMOS-to0.7V HCSL Fanout Buffer

Description

The 85105I is a low skew, high performance 1-to-5 Differential-to0.7V HCSL Fanout Buffer.

The 85105I has two selectable clock inputs.

The CLK0, nCLK0 pair can accept most standard differential input levels.

Features

  • Five 0.7V differential HCSL outputs.
  • Selectable differential CLK0, nCLK0 or LVCMOS inputs.
  • CLK0, nCLK0 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL.
  • CLK1 can accept the following input levels: LVCMOS or LVTTL.
  • Maximum output frequency: 500MHz.
  • Translates any single-ended input signal to 3.3V HCSL levels with resistor bias on nCLK input.
  • Output skew: 100ps (maximum).
  • Part-to-part skew:.

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Datasheet preview – 85105I

Datasheet Details

Part number 85105I
Manufacturer Renesas
File Size 380.59 KB
Description Differential/LVCMOS-to0.7V HCSL Fanout Buffer
Datasheet download datasheet 85105I Datasheet
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Low Skew, 1-to-5, Differential/LVCMOS-to0.7V HCSL Fanout Buffer 85105I Data Sheet GENERAL DESCRIPTION The 85105I is a low skew, high performance 1-to-5 Differential-to0.7V HCSL Fanout Buffer. The 85105I has two selectable clock inputs. The CLK0, nCLK0 pair can accept most standard differential input levels. The single-ended CLK1 can accept LVCMOS or LVTTL input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/ deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 85105I ideal for those applications demanding well defined performance and repeatability. FEATURES • Five 0.
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