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854S057B - 4:1 or 2:1 LVDS Clock Multiplexer

Description

The 854S057B is a 4:1 or 2:1 LVDS Clock Multiplexer which can operate up to 2GHz.

The PCLK, nPCLK pairs can accept most standard differential input levels.

Internal termination is provided on each differential input pair.

Features

  • High speed differential multiplexer. The device can be configured as either a 4:1 or 2:1 multiplexer.
  • One LVDS output pair.
  • Four selectable PCLK, nPCLK inputs with internal termination.
  • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL.
  • Maximum output frequency: >2GHz.
  • Part-to-part skew: 200ps (maximum).
  • Propagation delay: 800ps (maximum).
  • Additive phase jitter, RMS: 0.065ps (ty.

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Datasheet Details

Part number 854S057B
Manufacturer Renesas
File Size 742.94 KB
Description 4:1 or 2:1 LVDS Clock Multiplexer
Datasheet download datasheet 854S057B Datasheet
Additional preview pages of the 854S057B datasheet.

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Full PDF Text Transcription

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4:1 or 2:1 LVDS Clock Multiplexer with Internal Input Termination 854S057B Datasheet General Description The 854S057B is a 4:1 or 2:1 LVDS Clock Multiplexer which can operate up to 2GHz. The PCLK, nPCLK pairs can accept most standard differential input levels. Internal termination is provided on each differential input pair. The 854S057B operates using a 2.5V supply voltage. The fully differential architecture and low propagation delay make it ideal for use in high speed multiplexing applications. The select pins have internal pulldown resistors. Leaving one input unconnected (pulled to logic low by the internal resistor) will transform the device into a 2:1 multiplexer.
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