873996 Overview
The 873996 is a Zero Delay/Multiplier/Divider with hitless input clock switching capability and a member of the family of low jitter/phase noise devices from IDT. The 873996 is ideal for use in redundant, fault tolerant clock trees where low phase noise and low jitter are critical. The device receives two differential LVPECL clock signals from which it generates 6 LVPECL clock outputs with “zero” delay.
873996 Key Features
- Six differential 3.3V LVPECL outputs
- Selectable differential clock inputs
- CLKx, nCLKx pair can accept the following differential
- Input clock frequency range: 49MHz to 213.33MHz
- Output clock frequency range: 49MHz to 640MHz
- VCO range: 490MHz to 640MHz
- External feedback for “zero delay” clock regeneration
- Output skew: 100ps (maximum)
- RMS phase jitter (1.875MHz
- 20MHz): 0.6ps (typical) assum