89HPES12N3A Datasheet | Renesas

Overview The 89HPES12N3A is a member of the IDT PRECISE™ family of PCI Express® switching solutions. The PES12N3A is a 12-lane, 3-port peripheral chip that performs PCI Express packet switching with a feature set optimized for high performance applications such as servers, storage, and munications/networking. It provides connectivity and switching functions between a PCI Express upstream port and two downstream ports and supports switching between downstream ports. Features - High Performance PCI Express Switch - Twelve 2.5Gbps PCI Express lanes - Three switch ports - Upstream port configurable up to x4 - Downstream ports configurable up to x4 - Low-latency cut-through switch architecture - Support for Max Payload Sizes up to 2048 bytes - One virtual channel - Eight traffic classes - PCI Express Base Specification Revision 1.1 pliant - Flexible Architecture with Numerous Configuration Options - Automatic per port link width negotiation to x4, x2 or x1 - Automatic lane reversal on all ports - Automatic polarity inversion on all lanes - Ability to load device configuration from serial EEPROM - Legacy Support - PCI patible INTx emulation - Bus locking - Highly Integrated Solution - Requires no external ponents - Incorporates on-chip internal memory for packet buffering and queueing - Integrates twelve 2.5 Gbps embedded Ser Des with 8B/10B encoder/decoder (no separate transceivers needed) - Reliability, Availability, and Serviceability (RAS) Features - Supports ECRC and Advanced Error Reporting - Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC) - Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O - patible with Hot-Plug I/O expanders used on PC and server motherboards Block Diagram Frame Buffer 3-Port Switch Core Route Table Port Arbitration SScchheedduulelerr Transaction Layer Data Link Layer Multiplexer/Demultiplexer Phy Logical Layer Phy Logical...