Description
The 8A34002 is a Synchronization Management Unit (SMU) for packet based and physical layer based equipment synchronization.
Features
- Four independent timing channels.
- Each can act as a frequency synthesizer, jitter attenuator,
Digitally Controlled Oscillator (DCO), or Digital Phase Lock Loop (DPLL).
- DPLLs generate telecom compliant clocks.
- Compliant with ITU-T G.8262 for Synchronous Ethernet.
- Compliant with legacy SONET/SDH and PDH
requirements.
- DPLL Digital Loop Filters (DLFs) are programmable with cut
off frequencies from 12µHz to 22kHz.
- DPLL/DCO channels share frequency i.
8A34002 Datasheet
