8P34S2106 Datasheet | Renesas

Description The 8P34S2106 is a high-performance, low-power, differential dual 1:6 LVDS output 1.8V/2.5V fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. Two independent buffer channels are available, each channel has six low skew outputs. High isolation between channels minimizes noise coupling. AC characteristics such as propagation delay are matched between channels. Guaranteed output-to-output and part-to-part skew characteristics make the 8P34S2106 ideal for those clock distribution applications demanding well-defined performance and repeatability. The device is characterized to operate from a 1.8V/2.5V power supply. The integrated bias voltage references enable easy interfacing of AC-coupled signals to the device inputs. Block Diagram VDDA CLKA n CLKA 51k 51k 51k VREFA Voltage Reference A VDDA 51k SELAA VDDB 51k CLKB n CLKB 51k 51k VREFB Voltage Reference B VDDB 51k SELAB QA0 n QA0 QA1 n QA1 QA2 n QA2 QA3 n QA3 QA4 n QA4 QA5 n QA5 QB0 n QB0 QB1 n QB1 QB2 n QB2 QB3 n QB3 QB4 n QB4 QB5 n QB5 Features - Dual 1:6 low skew, low additive jitter LVDS fanout buffers - Matched AC characteristics across both channels - High isolation between channels - Low power consumption - Both differential CLKA, n CLKA and CLKB, n CLKB inputs accept LVDS, LVPECL and single-ended LVCMOS levels - Maximum input clock frequency:...