8SLVD1212 Description
The 8SLVD1212 is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVD1212 is characterized to operate from a 2.5V power supply.
8SLVD1212 Key Features
- Twelve low skew, low additive jitter LVDS output pairs
- Two selectable, differential clock input pairs
- Differential PCLK, nPCLK pairs can accept the following
- Maximum input clock frequency: 2GHz (maximum)
- LVCMOS/LVTTL interface levels for the control input select
- Output skew: 40ps (maximum)
- Propagation delay: 310ps (typical)
- Low additive phase jitter, RMS; fREF = 156.25MHz
- Device current consumption (IDD): 213mA (maximum)
- 2.5V supply voltage