8SLVD1212 Datasheet | Renesas

Description The 8SLVD1212 is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVD1212 is characterized to operate from a 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the device ideal for clock distribution applications that demand well-defined performance and repeatability. Two selectable differential inputs and twelve low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The 8SLVD1212 is optimized for low power consumption and low additive phase noise. Block Diagram Features - Twelve low skew, low additive jitter LVDS output pairs - Two selectable, differential clock input pairs - Differential PCLK, n PCLK pairs can accept the following differential input levels: LVDS, LVPECL, CML - Maximum input clock frequency: 2GHz (maximum) - LVCMOS/LVTTL interface levels for the control input select pins - Output skew: 40ps (maximum) - Propagation delay: 310ps (typical) - Low additive phase jitter, RMS; f REF = 156.25MHz, 10k Hz to 20MHz: 77fs (typical) - Device current consumption (IDD): 213m A (maximum) - 2.5V supply voltage - Lead-free (Ro HS 6), 6 6 mm, 40-VFQFN packaging - -40°C to 85°C ambient operating temperature VREF0 Voltage Reference PCLK0 n PCLK0 GND VDD PCLK1 n PCLK1 SEL f REF VDD VREF1 Voltage Reference Q0 n Q0 Q1 n Q1 Q2 n Q2 Q3 n Q3 Q4 n Q4 Q5 n Q5 Q6 n Q6 Q7 n Q7 Q8 n Q8 Q9 n Q9 Q10 n Q10 Q11 n Q11 ©2021 Renesas Electronics Corporation February 2, 2021 8SLVD1212 Datasheet Contents Description - - - - - - -...