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8SLVP1102 - 2.5V LVPECL Output Fanout Buffer

General Description

The 8SLVP1102 is a high-performance differential LVPECL fanout buffer.

The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals.

The 8SLVP1102 is characterized to operate from a 3.3V or 2.5V power supply.

Key Features

  • Two low skew, low additive jitter LVPECL output pairs.
  • Differential PCLK, nPCLK pair can accept the following differential input levels: LVDS, LVPECL, CML.
  • Maximum input clock frequency: 2GHz.
  • Output skew: 5ps (typical).
  • Propagation delay: 250ps (maximum).
  • Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V, 12kHz.
  • 20MHz: 49fs (maximum).
  • Full 3.3V or 2.5V supply voltage.
  • Maximum device current consumption (IEE.

📥 Download Datasheet

Datasheet Details

Part number 8SLVP1102
Manufacturer Renesas
File Size 0.97 MB
Description 2.5V LVPECL Output Fanout Buffer
Datasheet download datasheet 8SLVP1102 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Low Phase Noise, 1-to-2, 3.3V, 2.5V LVPECL Output Fanout Buffer 8SLVP1102 Datasheet Description The 8SLVP1102 is a high-performance differential LVPECL fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVP1102 is characterized to operate from a 3.3V or 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVP1102 ideal for those clock distribution applications demanding well-defined performance and repeatability. One differential input and two low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device input. The device is optimized for low power consumption and low additive phase noise.