8SLVP1212 Datasheet | Renesas

Description The 8SLVP1212 is a high-performance, 12 output differential LVPECL fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVP1212 is characterized to operate from a 3.3V and 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVP1212 ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and twelve low skew outputs are available. The integrated bias voltage generators enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise. Block Diagram PCLK0 n PCLK0 f REF VCC PCLK1 n PCLK1 SEL VREF Voltage Reference Q0 n Q0 Q1 n Q1 Q2 n Q2 Q3 n Q3 Q4 n Q4 Q5 n Q5 Q6 n Q6 Q7 n Q7 Q8 n Q8 Q9 n Q9 Q10 n Q10 Q11 n Q11 Features - Twelve low skew, low additive jitter LVPECL outputs - Two selectable, differential clock inputs - Differential pairs can accept the following differential input levels: LVDS, LVPECL, CML - Maximum input clock frequency: 2GHz - LVCMOS interface levels for the control input (input select) - Output skew: 33ps (maximum) - Propagation delay: 550ps (maximum) - Low additive phase jitter, RMS at f REF = 156.25MHz, VPP = 1V, 12k Hz- 20MHz: 60fs (maximum) - Full 3.3V and 2.5V supply voltage - Device current consumption (IEE): 131m A (maximum) - Available in Lead-free (Ro HS 6), 40-VFQFPN package - -40°C to +85°C ambient operating temperature - Differential PCLK0, n PCLK0 and PCLK1, n PCLK1 pairs can also accept single-ended LVCMOS levels. See Applications section Wiring the Differential Input Levels to Accept Single-ended Levels (Figure 1A and Figure 1B) - Supports PCI Express Gen1- 5 Pin Assignment Q4 n Q4 Q5 n Q5 Q6 n Q6 Q7 n Q7 30 29 28 27 26 25 24 23 22 21 VCC 31 20 VCC Q8 32 19 n Q3 n Q8 33 18 Q3 Q9 34 17 n Q2 n Q9...