8T73S208B-01
Description
The 8T73S208B-01 is a high-performance differential LVPECL clock divider and fanout buffer.
Key Features
- One differential input reference clock
- Differential pair can accept the following differential input levels: LVDS, LVPECL, CML
- Integrated input termination resistors
- Eight LVPECL outputs
- Maximum input clock frequency: 1GHz
- LVCMOS interface levels for the control inputs
- Individual output enable/disabled by I2C interface
- Power-up state: all outputs disabled
- Output skew: 60ps (maximum)
- Output rise/fall times: 350ps (maximum)
