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8T73S208B-01 - Differential LVPECL Clock Divider and Fanout Buffer

Datasheet Summary

Description

The 8T73S208B-01 is a high-performance differential LVPECL clock divider and fanout buffer.

The device is designed for the frequency division and signal fanout of high-frequency, low phase-noise clocks.

The 8T73S208B-01 is characterized to operate from a 2.5V and 3.3V power supply.

Features

  • One differential input reference clock.
  • Differential pair can accept the following differential input levels: LVDS, LVPECL, CML.
  • Integrated input termination resistors.
  • Eight LVPECL outputs.
  • Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8.
  • Maximum input clock frequency: 1GHz.
  • LVCMOS interface levels for the control inputs.
  • Individual output enable/disabled by I2C interface.
  • Power-up state: all outputs disa.

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Datasheet Details

Part number 8T73S208B-01
Manufacturer Renesas
File Size 559.66 KB
Description Differential LVPECL Clock Divider and Fanout Buffer
Datasheet download datasheet 8T73S208B-01 Datasheet
Additional preview pages of the 8T73S208B-01 datasheet.

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Full PDF Text Transcription

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2.5 V, 3.3 V Differential LVPECL Clock Divider and Fanout Buffer 8T73S208B-01 Datasheet General Description The 8T73S208B-01 is a high-performance differential LVPECL clock divider and fanout buffer. The device is designed for the frequency division and signal fanout of high-frequency, low phase-noise clocks. The 8T73S208B-01 is characterized to operate from a 2.5V and 3.3V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8T73S208B-01 ideal for those clock distribution applications demanding well-defined performance and repeatability. The integrated input termination resistors make interfacing to the reference source easy and reduce passive component count.
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