8T73S208B-01 - Differential LVPECL Clock Divider and Fanout Buffer

Product Overview

Renesas

Part number	8T73S208B-01
Manufacturer	Renesas
File Size	559.66 KB
Description	Differential LVPECL Clock Divider and Fanout Buffer
Datasheet	8T73S208B-01 Datasheet
Additional preview pages of the 8T73S208B-01 datasheet.

The 8T73S208B-01 is a high-performance differential LVPECL clock divider and fanout buffer.

One differential input reference clock.
Differential pair can accept the following differential input levels: LVDS, LVPECL, CML.
Integrated input termination resistors.
Eight LVPECL outputs.
Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8.
Maximum input clock frequency: 1GHz.
LVCMOS interface levels for the control inputs.
Individual output enable/disabled by I2C interface.
Power-up state: all outputs disa.

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Published: Jun 4, 2020 |