8T74S208A-01 - LVDS Clock Divider and Fanout Buffer

Product Overview

Renesas

Part number	8T74S208A-01
Manufacturer	Renesas
File Size	532.57 KB
Description	LVDS Clock Divider and Fanout Buffer
Datasheet	8T74S208A-01 Datasheet
Additional preview pages of the 8T74S208A-01 datasheet.

The 8T74S208A-01 is a high-performance differential LVDS clock divider and fanout buffer.

One differential input reference clock Differential pair can accept the following differential input levels: LVDS, LVPECL, CML Integrated input termination resistors Eight LVDS outputs Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8 Maximum input clock frequency: 1GHz LVCMOS interface levels for the control inputs Individual output enabled/ disabled by I2C interface Output skew: 45ps (maximum) Output rise/fall times: 370ps (maximum) Low additive phase jitter, RMS: 96fs (typical) Full 2.

📁 Similar Datasheet

8T74S208A-01 - 2.5V Differential LVDS Clock Divider and Fanout Buffer (IDT)
8T74S208 - 2.5V Differential LVDS Clock Divider and Fanout Buffer (IDT)
8T74S208C-01 - 2.5 V Differential LVDS Clock Divider and Fanout Buffer (IDT)
8T73S1802 - 1:2 Clock Fanout Buffer and Frequency Divider (Integrated Device Technology)
8T73S208 - Differential LVPECL Clock Divider and Fanout Buffer (Integrated Device Technology)
8T73S208A-01 - LVPECL Clock Divider and Buffer (IDT)
8T73S208B-01 - LVPECL Clock Divider and Fanout Buffer (IDT)
8T79S308 - 1:8 Universal Differential Fanout Buffer (IDT)

Other Datasheets by Renesas

Published: Jun 4, 2020 |