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8T74S208A-01 - LVDS Clock Divider and Fanout Buffer

Datasheet Summary

Description

The 8T74S208A-01 is a high-performance differential LVDS clock divider and fanout buffer.

The device is designed for the frequency division and signal fanout of high-frequency, low phase-noise clocks.

The 8T74S208A-01 is characterized to operate from a 2.5V power supply.

Features

  • One differential input reference clock Differential pair can accept the following differential input levels: LVDS, LVPECL, CML Integrated input termination resistors Eight LVDS outputs Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8 Maximum input clock frequency: 1GHz LVCMOS interface levels for the control inputs Individual output enabled/ disabled by I2C interface Output skew: 45ps (maximum) Output rise/fall times: 370ps (maximum) Low additive phase jitter, RMS: 96fs (typical) Full 2.

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Datasheet Details

Part number 8T74S208A-01
Manufacturer Renesas
File Size 532.57 KB
Description LVDS Clock Divider and Fanout Buffer
Datasheet download datasheet 8T74S208A-01 Datasheet
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Full PDF Text Transcription

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2.5V Differential LVDS Clock Divider and Fanout Buffer 8T74S208A-01 REFER TO PCN# N1608-01, Effective Date November 18, 2016 FOR NEW DESIGNS USE PART NUMBER 8T74S208C-01 DATA SHEET General Description The 8T74S208A-01 is a high-performance differential LVDS clock divider and fanout buffer. The device is designed for the frequency division and signal fanout of high-frequency, low phase-noise clocks. The 8T74S208A-01 is characterized to operate from a 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8T74S208A-01 ideal for those clock distribution applications demanding well-defined performance and repeatability. The integrated input termination resistors make interfacing to the reference source easy and reduce passive component count.
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