Renesas Electronics 97ULPA877A
The Logic Detect (LD) powers down the device when a logic low is applied to both CLK_INT and CLK_INC. The clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT, FB_INC), the LVCMOS program pins (OE, OS) and the Analog Power input (AVDD).When OE is low, the outputs (except FB_OUTT/FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency.| Part No. | 97ULPA877A |
|---|---|
| Datasheet | 97ULPA877A Download |
| Manufacturer |  Renesas Electronics |
| Description | 1.8V Low-Power Wide-Range Frequency Clock Driver |
| Buy | Stock & Price |
DESCRIPTION
/FEATURES
:● Low skew, low jitter PLL clock driver
● 1 to 10 differential clock distribution (SSTL_18)
● Feedback pins for input to output synchronization
● Spread Spectrum tolerant inputs
● Auto PD when input signal is at a certain logic state Switching Characteristics:
● Period jitter: 40ps (DDR2-400/533) 30ps (DDR2-667/800)
● Half-period jitter: 60ps (DDR2-400/533) 50ps (DDR2-667/800)
● OUTPUT - OUTPUT skew: 40ps (DDR2-400/533) 30ps (DDR2-667/800)
● CYCLE - CYCLE jitter 40ps Block Diagram Pin Configuration 123456 A B C D E F G H J K 52-Ball BGA Top View 1 A CLKT1 B CLKC1 C CLKC2 D CLKT2 E CLK_INT F CLK_INC G AGND H AVDD J CLKT3 K CLKC3 2 CLKT0 GND GND VDDQ VDDQ VDDQ VDDQ GND GND CLKC4 3 CLKC0 GND NB VDDQ NB NB VDDQ NB GND CLKT4 4 CLKC5 GND NB VDDQ NB NB VDDQ NB GND CLKT9 5 CLKT5 G ND G ND OS VDDQ OE VDDQ G ND G ND CLKC9 6 CLKT6 CLKC6 CLKC7 CLKT7 FB_INT FB_INC FB_OUTC FB_OUTT CLKT8 CLKC8 OE OS AVDD Powerdown Control and Test Logic LD* or OE LD*, OS or OE LD* PLL bypass CLK...
