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9DBV0231 - 2-Output 1.8V PCIe Zero-Delay/Fanout Clock Buffer

Datasheet Summary

Description

The 9DBV0231 is a member of Renesas’ 1.8V Very-Low-Power (VLP) PCIe family.

The device has 2 output enables for clock management.

5 Zero-Delay/Fan-out Buffer (ZDB/FOB) Output

Features

  • Two 1.
  • 200MHz Low-Power (LP) HCSL DIF pairs Key Specifications.
  • DIF cycle-to-cycle jitter < 50ps.
  • DIF output-to-output skew < 50ps.
  • PCIe Gen5 CC additive phase jitter < 40fs RMS.
  • 12kHz.
  • 20MHz additive phase jitter = 156fs RMS at 156.25MHz (typical) Block Diagram Features/Benefits.
  • LP-HCSL outputs; save 4 resistors compared to standard HCSL outputs.
  • 35mW typical power consumption in PLL mode; reduced thermal concerns.

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Datasheet preview – 9DBV0231

Datasheet Details

Part number 9DBV0231
Manufacturer Renesas
File Size 717.00 KB
Description 2-Output 1.8V PCIe Zero-Delay/Fanout Clock Buffer
Datasheet download datasheet 9DBV0231 Datasheet
Additional preview pages of the 9DBV0231 datasheet.

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Full PDF Text Transcription

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2-Output 1.8V PCIe Zero-Delay/Fanout Clock Buffer with Zo = 33Ohms 9DBV0231 DATASHEET Description The 9DBV0231 is a member of Renesas’ 1.8V Very-Low-Power (VLP) PCIe family. The device has 2 output enables for clock management. Recommended Application 1.8V PCIe Gen1–5 Zero-Delay/Fan-out Buffer (ZDB/FOB) Output Features • Two 1–200MHz Low-Power (LP) HCSL DIF pairs Key Specifications • DIF cycle-to-cycle jitter < 50ps • DIF output-to-output skew < 50ps • PCIe Gen5 CC additive phase jitter < 40fs RMS • 12kHz–20MHz additive phase jitter = 156fs RMS at 156.
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