9DBV0441 Description
The 9DBV0441 is a member of Renesas’ SOC-Friendly 1.8V Very-Low-Power (VLP) PCIe family. It has integrated output terminations providing Zo = 100 for direct connection to 100 transmission lines. The device has 4 output enables for clock management, and 3 selectable SMBus addresses.
9DBV0441 Key Features
- DIF cycle-to-cycle jitter < 50ps
- DIF output-to-output skew < 50ps
- PCIe Gen5 CC additive phase jitter < 40fs RMS
- 12kHz-20MHz additive phase jitter = 156fs RMS at
- Direct connection to 100 transmission lines; saves 16
- 53mW typical power consumption in PLL mode; minimal
- OE# pins; support DIF power management
- HCSL patible differential input; can be driven by
- Programmable Slew rate for each output; allows tuning
- Pin/software selectable PLL bandwidth and PLL Bypass