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9DBV0441 - 1.8V PCIe Gen1-4 ZDB/FOB

General Description

The 9DBV0441 is a member of Renesas’ SOC-Friendly 1.8V Very-Low-Power (VLP) PCIe family.

It has integrated output terminations providing Zo = 100 for direct connection to 100 transmission lines.

The device has 4 output enables for clock management, and 3 selectable SMBus addresses.

Key Features

  • Four 1.
  • 200MHz Low-Power (LP) HCSL DIF pairs with ZO = 100 Key Specifications.
  • DIF cycle-to-cycle jitter < 50ps.
  • DIF output-to-output skew < 50ps.
  • PCIe Gen5 CC additive phase jitter < 40fs RMS.
  • 12kHz.
  • 20MHz additive phase jitter = 156fs RMS at 156.25MHz (typical) Block Diagram vOE(3:0)# Features/Benefits.
  • Direct connection to 100 transmission lines; saves 16 resistors compared to standard HCSL outputs.
  • 53mW typical.

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Datasheet Details

Part number 9DBV0441
Manufacturer Renesas
File Size 689.24 KB
Description 1.8V PCIe Gen1-4 ZDB/FOB
Datasheet download datasheet 9DBV0441 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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4-Output 1.8V PCIe Zero-Delay/Fanout Clock Buffer with Zo = 100ohms 9DBV0441 Datasheet Description The 9DBV0441 is a member of Renesas’ SOC-Friendly 1.8V Very-Low-Power (VLP) PCIe family. It has integrated output terminations providing Zo = 100 for direct connection to 100 transmission lines. The device has 4 output enables for clock management, and 3 selectable SMBus addresses. Typical Applications • 1.8V PCIe Gen1–5 Zero-Delay/Fan-out Buffer (ZDB/FOB) Output Features • Four 1–200MHz Low-Power (LP) HCSL DIF pairs with ZO = 100 Key Specifications • DIF cycle-to-cycle jitter < 50ps • DIF output-to-output skew < 50ps • PCIe Gen5 CC additive phase jitter < 40fs RMS • 12kHz–20MHz additive phase jitter = 156fs RMS at 156.