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9DBV0641 Datasheet PDF

Renesas Electronics 9DBV0641

The 9DBV0641 is a member of Renesas’ 1.8V Very-Low-Power (VLP) PCIe family. It has integrated output terminations providing Zo = 100 for direct connection to 100 transmission lines. The device has 6 output enables for clock management and 3 selectable SMBus addresses.
Part No. 9DBV0641
Datasheet 9DBV0641 Download
Manufacturer
Renesas Electronics
Description 6-Output 1.8V PCIe Zero-Delay/Fanout Clock Buffer
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9DBV0641 datasheet page 1 preview

DESCRIPTION

It has integrated output terminations providing Zo = 100 for direct connection to 100 transmission lines. Recommended Application 1.8V PCIe Gen1–5 Zero Delay/Fanout Buffer (ZDB/FOB) Output

FEATURES

● Six 1–200 MHz Low-Power (LP) HCSL DIF pairs with Zo = 100 Key Specifications
● DIF cycle-to-cycle jitter < 50ps
● DIF output-to-output skew < 50ps
● PCIe Gen5 CC additive phase jitter < 40fs RMS
● 12kHz–20MHz additive phase jitter = 156fs RMS at 156.25MHz (typical) Block Diagram vOE(5:0)# 6

FEATURES

/Benefits
● Direct connection to 100 transmission lines; saves 24 resistors compared to standard PCIe devices
● 55mW typical power consumption in PLL mode; minimal power consumption
● Outputs can optionally be supplied from any voltage between 1.05 and 1.8V; maximum power savings
● OE# pins; support DIF power management
● HCSL compatible differential input; can be driven by common clock sources
● Spread Spectrum tolerant; allows reduction of EMI
● Programmable Slew rate for each...
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