Renesas Electronics 9LP525-2
The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus.| Part No. | 9LP525-2 |
|---|---|
| Datasheet | 9LP525-2 Download |
| Manufacturer |  Renesas Electronics |
| Description | 56-pin CK505 Clock |
| Buy | Stock & Price |
FEATURES
:● 2 - CPU differential low power push-pull pairs
● 7- SRC differential low power push-pull pairs
● 1 - CPU/SRC selectable differential low power push-pull pair
● 1 - SRC/DOT selectable differential low power push-pull pair
● 5 - PCI, 33MHz
● 1 - PCI_F, 33MHz free running
● 1 - USB, 48MHz
● 1 - REF, 14.318MHz Key Specifications:
● CPU outputs cycle-cycle jitter < 85ps
● SRC output cycle-cycle jitter < 125ps
● PCI outputs cycle-cycle jitter < 250ps
● +/- 100ppm frequency accuracy on all outputs
● SRC are PCIe Gen2 compliant
FEATURES
/Benefits:● Supports spread spectrum modulation, default is 0.5% down spread
● Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning
● Selectable SRC differential push-pull pair/two single ended outputs Table 1: CPU Frequency Select Table FSLC2 B0b7 0 0 0 0 1 1 1 1 FSLB1 B0b6 0 0 1 1 0 0 1 1 FSLA1 B0b5 0 1 0 1 0 1 0 1 CPU MHz 266.66 133.33 200.00 166.66 333.33 100.00 400.00 SRC PCI REF USB DOT MHz MHz MHz MHz MHz 100.00 33.33 14.318 48.00 96.00 Reserved 1.
