9Z61195D Description
The 9Z61195D is a second-generation, enhanced-performance DB1900Z derivative differential buffer. The part is a pin-patible upgrade to the 9Z61195A, offering much improved phase jitter performance. A fixed external feedback maintains low drift for critical QPI/UPI applications.
9Z61195D Key Features
- 19 Low-Power (LP) HCSL output pairs with 85Ω Zout
- LP-HCSL outputs with 85Ω Zout; eliminate 76 resistors, save 130mm2 of area
- SMBus OE bits; software control of each output
- 9 selectable SMBus addresses; multiple devices can share
- Hardware/SMBus control of PLL bandwidth and bypass
- 10 × 10 mm 72-VFQFPN package; small board footprint
- Cycle-to-cycle jitter: < 50ps
- Output-to-output skew: < 50ps
- Input-to-output delay: Fixed at 0ps
- Input-to-output delay variation: < 50ps