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HD74ACT112 - Dual JK Negative Edge-Triggered Flip-Flop

Download the HD74ACT112 datasheet PDF. This datasheet also covers the HD74AC112 variant, as both devices belong to the same dual jk negative edge-triggered flip-flop family and are provided as variant models within a single manufacturer datasheet.

General Description

The HD74AC112/HD74ACT112

Key Features

  • individual J, K, Clock and asynchronous Set and Clear inputs to each flipflop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may change when the clock is High and the bistable will perform according to the Truth Table as long as minimum setup and hold times are observed. Input data is transferred to the outputs on the falling edge of the clock pulse. Features.
  • Outputs Source/Sink 24 mA.
  • HD74ACT112 has TTL-Comp.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (HD74AC112-Renesas.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number HD74ACT112
Manufacturer Renesas
File Size 209.33 KB
Description Dual JK Negative Edge-Triggered Flip-Flop
Datasheet download datasheet HD74ACT112 Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
HD74ACT112 Dual JK Negative Edge-Triggered Flip-Flop Hitachi Semiconductor
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HD74ACT125 Quad Buffer/Line Driver with 3-State Output Hitachi Semiconductor
HD74ACT126 Quad Buffer/Line Driver with 3-State Output Hitachi Semiconductor
HD74ACT138 1-of-8 Decoder/Demultiplexer Hitachi Semiconductor

Other Datasheets by Renesas

Part Number Description
HD74ACT107 Dual JK Flip-Flop
HD74ACT125 Quad Buffer/Line Driver
HD74ACT126 Quad Buffer/Line Driver
HD74ACT138 1-of-8 Decoder/Demultiplexer
HD74ACT139 Dual 1-of-4 Decoder/Demultiplexer

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
HD74AC112/HD74ACT112 Dual JK Negative Edge-Triggered Flip-Flop REJ03D0244–0200Z (Previous ADE-205-364 (Z)) Rev.2.00 Jul.16.2004 Description The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to each flipflop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may change when the clock is High and the bistable will perform according to the Truth Table as long as minimum setup and hold times are observed. Input data is transferred to the outputs on the falling edge of the clock pulse. Features • Outputs Source/Sink 24 mA • HD74ACT112 has TTL-Compatible Inputs • Ordering Information: Ex.