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HD74ALVCH162827 - 20-bit Buffers / Drivers

General Description

The HD74ALVCH162827 is composed of two 10-bit sections with separate output enable signals.

For either 10-bit buffer section, the two output enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must both be low for the corresponding Y outputs to be active.

Key Features

  • VCC = 2.3 V to 3.6 V.
  • Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C).
  • Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C).
  • High output current ±12 mA (@VCC = 3.0 V).
  • Bus hold on data inputs eliminates the need for external pullup / p.

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📁 Similar Datasheet

Part Number Description Manufacturer
HD74ALVCH162827 20-bit Buffers / Drivers with 3-state Outputs Hitachi Semiconductor
HD74ALVCH162820 3.3-V 10-bit Flip Flops with Dual Outputs and 3-state Outputs Hitachi Semiconductor
HD74ALVCH162821 3.3-V 20-bit Bus Interface Flip Flops with 3-state Outputs Hitachi Semiconductor
HD74ALVCH162825 18-bit Buffers / Drivers with 3-state Outputs Hitachi Semiconductor
HD74ALVCH162830 1-bit to 2-bit Address Driver with 3-state Outputs Hitachi Semiconductor

Other Datasheets by Renesas

Part Number Description
HD74ALVCH162830 1-bit to 2-bit Address Driver
HD74ALVCH162831 1-bit 4-bit Address Register / Driver
HD74ALVCH162244 16-bit Buffers / Drivers
HD74ALVCH162270 12-bit to 24-bit Registered Bus Exchanger
HD74ALVCH16244 16-bit Buffers / Drivers

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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HD74ALVCH162827 20-bit Buffers / Drivers with 3-state Outputs REJ03D0042-0400Z (Previous ADE-205-188B (Z) ) Rev.4.00 Oct.02.2003 Description The HD74ALVCH162827 is composed of two 10-bit sections with separate output enable signals. For either 10-bit buffer section, the two output enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must both be low for the corresponding Y outputs to be active. If either output enable input is high, the outputs of that 10-bit buffer section are in the high impedance state. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. All outputs, which are designed to sink up to 12 mA, include 26 Ω resistors to reduce overshoot and undershoot. Features • VCC = 2.3 V to 3.6 V • Typical VOL ground bounce < 0.8 V (@VCC = 3.