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HD74HC165 - Parallel-load 8-bit Shift Register

General Description

This 8-bit serial shift register shifts data from QA to QH when clocked.

Parallel inputs to each stage are enabled by a low level at the Shift/Load input.

Also included is a gated clock input and a complementary output from the eighth bit.

Key Features

  • High Speed Operation: tpd (Clock to QH) = 21 ns typ (CL = 50 pF).
  • High Output Current: Fanout of 10 LSTTL Loads.
  • Wide Operating Voltage: VCC = 2 to 6 V.
  • Low Input Current: 1 µA max.
  • Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C).
  • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation HD74HC165P DILP-16 pin PRDP0016AE-B (DP-16FV) P HD74HC165FPEL SOP-16 pin (JEITA) PRSP0016DH.

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Datasheet Details

Part number HD74HC165
Manufacturer Renesas
File Size 86.31 KB
Description Parallel-load 8-bit Shift Register
Datasheet download datasheet HD74HC165 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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HD74HC165 Parallel-load 8-bit Shift Register REJ03D0581-0300 Rev.3.00 Jan 31, 2006 Description This 8-bit serial shift register shifts data from QA to QH when clocked. Parallel inputs to each stage are enabled by a low level at the Shift/Load input. Also included is a gated clock input and a complementary output from the eighth bit. Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a clock inhibit function. Holding either of the clock inputs high inhibits clocking, and holding either clock input low with the Shift/Load input high enables the other clock input. Data transfer occurs on the positive going edge of the clock. Parallel loading is inhibited as long as the Shift/Load input is high.