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HD74HC4024 - 7-stage Binary Counter

General Description

The HD74HC4024 is a 7-stage counter.

This device is incremented on the falling edge (negative transition) of the input clock, and all its output is reset to a low level by applying a logical high on its reset input.

Key Features

  • High Speed Operation: tpd (Clock to Q1) = 14 ns typ (CL = 50 pF).
  • High Output Current: Fanout of 10 LSTTL Loads.
  • Wide Operating Voltage: VCC = 2 to 6 V.
  • Low Input Current: 1 µA max.
  • Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C).
  • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation HD74HC4024P DILP-14 pin PRDP0014AB-B (DP-14AV) P HD74HC4024FPEL SOP-14 pin (JEITA) PRSP0014.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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HD74HC4024 7-stage Binary Counter REJ03D0325-0300 Rev.3.00 Mar 30, 2006 Description The HD74HC4024 is a 7-stage counter. This device is incremented on the falling edge (negative transition) of the input clock, and all its output is reset to a low level by applying a logical high on its reset input.