HD74HC85
Description
The HD74HC85 is designed for high speed parison of two four bit words. This circuit has eight parison input, 4 for each word; three cascade inputs (A < B, A > B, A = B); and three decision outputs (A < B, A > B, A = B). The result of a parison is indicated by a high level on one of the decision outputs. Thus it may be determined whether one word is “greater than,” “less than,” or “equal to” the other word. By connecting the outputs of the least significant stage to the cascade inputs of the next stage, words of greater than four bits can be pared. In addition the least significant stage must have a high level applied to the A = B input, and a low level to the A < B, and A > B inputs.
Features
- High Speed Operation: tpd (Data Word Input to Output) = 20 ns typ (CL = 50 p F)
- High Output Current: Fanout of 10 LSTTL Loads
- Wide Operating Voltage:...
