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HD74LS10P - Triple 3-Input Positive NAND Gates

Download the HD74LS10P datasheet PDF. This datasheet also covers the HD74LS10 variant, as both devices belong to the same triple 3-input positive nand gates family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation HD74LS10P DILP-14 pin PRDP0014AB-B (DP-14AV) P HD74LS10FPEL SOP-14 pin (JEITA) PRSP0014DF-B FP (FP-14DAV) HD74LS10RPEL SOP-14 pin (JEDEC) PRSP0014DE-A (FP-14DNV) RP Note: Please consult the sales office for the above package availability. Pin Arrangement REJ03D0396.
  • 0200 Rev.2.00 Feb.18.2005 Taping Abbreviation (Quantity).
  • EL (2,000 pcs/reel) EL (2,500 pcs/r.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (HD74LS10-Renesas.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number HD74LS10P
Manufacturer Renesas
File Size 154.92 KB
Description Triple 3-Input Positive NAND Gates
Datasheet download datasheet HD74LS10P Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
HD74LS10 Triple 3-input Positive NAND Gates Hitachi Semiconductor
HD74LS107A Dual J-K Negative-edge-triggered Flip-Flops Hitachi Semiconductor
HD74LS109 Dual J-K Positive-edge-triggered Flip-Flops Hitachi Semiconductor
HD74LS109A Dual J-K Positive-edge-triggered Flip-Flops Hitachi Semiconductor
HD74LS11 Triple 3-input Positive AND Gates Hitachi Semiconductor

Other Datasheets by Renesas

Part Number Description
HD74LS10 Triple 3-Input Positive NAND Gates
HD74LS107A Dual J-K Negative-edge-triggered Flip-Flops
HD74LS107AP Dual J-K Negative-edge-triggered Flip-Flops
HD74LS11 Triple 3-input Positive AND Gates
HD74LS112 Dual J-K Negative-edge-triggered Flip-Flops

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
HD74LS10 Triple 3-Input Positive NAND Gates Features • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation HD74LS10P DILP-14 pin PRDP0014AB-B (DP-14AV) P HD74LS10FPEL SOP-14 pin (JEITA) PRSP0014DF-B FP (FP-14DAV) HD74LS10RPEL SOP-14 pin (JEDEC) PRSP0014DE-A (FP-14DNV) RP Note: Please consult the sales office for the above package availability. Pin Arrangement REJ03D0396–0200 Rev.2.00 Feb.18.2005 Taping Abbreviation (Quantity) — EL (2,000 pcs/reel) EL (2,500 pcs/reel) 1A 1 1B 2 2A 3 2B 4 2C 5 2Y 6 GND 7 14 VCC 13 1C 12 1Y 11 3C 10 3B 9 3A 8 3Y (Top view) Rev.2.00, Feb.18.2005, page 1 of 5 HD74LS10 Circuit Schematic (1/3) Inputs A B C VCC 8k 75 20k 4.5k Output Y 1.