Renesas Electronics HD74LS112P
Dual J-K Negative-edge-triggered Flip-Flops
| Part No. | HD74LS112P |
|---|---|
| Datasheet | HD74LS112P Download |
| Manufacturer |  Renesas Electronics |
| Description | Dual J-K Negative-edge-triggered Flip-Flops |
| Buy | Stock & Price |
FEATURES
● Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation HD74LS112P DILP-16 pin PRDP0016AE-B (DP-16FV) P HD74LS112FPEL SOP-16 pin (JEITA) PRSP0016DH-B FP (FP-16DAV) HD74LS112RPEL SOP-16 pin (JEDEC) PRSP0016DG-A (FP-16DNV) RP Note: Please consult the sales office for the above package availability. Taping Abbreviation (Quantity) — EL (2,000 pcs/reel) EL (2,500 pcs/reel) Pin Arrangement 1CK 1 1K 2 1J 3 1PR 4 1Q 5 1Q 6 2Q 7 GND 8 J CK K PR CLR Q Q K CK J CLR PR Q Q 16 VCC 15 1CLR 14 2CLR 13 2CK 12 2K 11 2J 10 2PR 9 2Q (Top view) Rev.3.00, Jul.13.2005, page 1 of 8 HD74LS112 Function Table Inputs Outputs Preset Clear Clock J K Q Q L H X X X H L H L X X X L H L L X X X H* H* H H ↓ L L QO QO H H ↓ H L H L H H ↓ L H L H H H ↓ H H Toggle H H H X X QO QO Notes: H; high level, L; low level, X; irrelevant ↓; transition from high to low level Q; level of Q before the indicated steady-state input conditions were established. Q; complement of QO or level of Q before the indicated steady-state input conditions were established.
