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HD74LS122P - Retriggerable Monostable Multivibrator

Download the HD74LS122P datasheet PDF. This datasheet also covers the HD74LS122 variant, as both devices belong to the same retriggerable monostable multivibrator family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • output pulse width control by three method. The basic pulse time is programmed by selection of external resistance and capacitance values. The HD74LS122 has internal timing resistor that allows the circuit to be used with only an external capacitor, if so desired. Once triggered, the basic pulse width may be extended by retriggering the gated low-level -active (A) or high-level active (B) inputs or be reduced by use of the overriding clear. Figure 1 illustrates pulse control by retriggering and.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (HD74LS122-Renesas.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number HD74LS122P
Manufacturer Renesas
File Size 204.80 KB
Description Retriggerable Monostable Multivibrator
Datasheet download datasheet HD74LS122P Datasheet

📁 Similar Datasheet

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Other Datasheets by Renesas

Part Number Description
HD74LS122 Retriggerable Monostable Multivibrator
HD74LS12 Triple 3-input Positive NAND Gates
HD74LS123 Dual Retriggerable Monostable Multivibrators
HD74LS123P Dual Retriggerable Monostable Multivibrators
HD74LS125A Quadruple Bus Buffer Gates

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
HD74LS122 Retriggerable Monostable Multivibrator (with Clear) REJ03D0428–0200 Rev.2.00 Feb.18.2005 This d-c triggered multivibrator features output pulse width control by three method. The basic pulse time is programmed by selection of external resistance and capacitance values. The HD74LS122 has internal timing resistor that allows the circuit to be used with only an external capacitor, if so desired. Once triggered, the basic pulse width may be extended by retriggering the gated low-level -active (A) or high-level active (B) inputs or be reduced by use of the overriding clear. Figure 1 illustrates pulse control by retriggering and early clear. This device is provided enough Schmitt hysteresis to ensure jitter-free triggering from the B input with transition rates as slow as 0.1 mV/ns.