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HD74LS164P - 8-Bit Parallel-Out Serial-in Shift Register

Download the HD74LS164P datasheet PDF. This datasheet also covers the HD74LS164 variant, as both devices belong to the same 8-bit parallel-out serial-in shift register family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • gated serial inputs and an asynchronous clear. The gated serial inputs (A and B) permit complete control over incoming data as a low at either (or both) input(s) inhibits entry of the new data and resets the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input which will them determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is high or low, but only information meeting the setup requirements will b.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (HD74LS164-Renesas.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number HD74LS164P
Manufacturer Renesas
File Size 85.57 KB
Description 8-Bit Parallel-Out Serial-in Shift Register
Datasheet download datasheet HD74LS164P Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
HD74LS164 8-Bit Parallel-Out Serial-In Shift Registers Hitachi Semiconductor
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HD74LS161A Synchronous 4-bit Binary Counters Hitachi Semiconductor
HD74LS162A Synchronous Decade Counters Hitachi Semiconductor
HD74LS163A Synchronous 4-bit Binary Counters Hitachi Semiconductor

Other Datasheets by Renesas

Part Number Description
HD74LS164 8-Bit Parallel-Out Serial-in Shift Register
HD74LS160A Synchronous Decade Counter
HD74LS160AP Synchronous Decade Counter
HD74LS161A Synchronous 4-bit Binary Counter
HD74LS161AP Synchronous 4-bit Binary Counter

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
HD74LS164 8-Bit Parallel-Out Serial-in Shift Register REJ03D0448–0200 Rev.2.00 Feb.18.2005 This 8-bit shift register features gated serial inputs and an asynchronous clear. The gated serial inputs (A and B) permit complete control over incoming data as a low at either (or both) input(s) inhibits entry of the new data and resets the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input which will them determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is high or low, but only information meeting the setup requirements will be entered. Clocking occurs on the low-to-high-level transition of the clock input.