Datasheet4U Logo Datasheet4U.com

HD74LV595A - 8-bit Shift Registers

General Description

This device each contains an 8-bit serial-in, parallel-out shift registers that feeds an 8-bit D-type storage register.

The storage register has parallel 3-state outputs.

Separate clocks are provided for both the shift register and the storage register.

Key Features

  • VCC = 2.0 V to 5.5 V operation.
  • All inputs VIH (Max. ) = 5.5 V (@VCC = 0 V to 5.5 V).
  • All output.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
HD74LV595A 8-bit Shift Registers with 3-state Outputs Hitachi Semiconductor
HD74LV540A Octal Inverted Buffers / Drivers with 3-state Outputs Hitachi Semiconductor
HD74LV541A Octal Buffers / Drivers with 3-state Outputs Hitachi Semiconductor
HD74LV573A Octal D-type Transparent Latches with 3-state Outputs Hitachi Semiconductor
HD74LV574A Octal Edge-Triggered D-type Flip-Flops with 3-state Outputs Hitachi Semiconductor

Other Datasheets by Renesas

Part Number Description
HD74LV540A Octal Inverted Buffers / Drivers
HD74LV541A Octal Buffers / Drivers
HD74LV573A Octal D-type Transparent Latches
HD74LV574A Octal D-type Flip-Flops
HD74LV00A 2-input NAND Gates

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
HD74LV595A 8-bit Shift Registers with 3-state Outputs REJ03D0335–0200Z (Previous ADE-205-281 (Z)) Rev.2.00 Jun. 28, 2004 Description This device each contains an 8-bit serial-in, parallel-out shift registers that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift register and the storage register. The shift register has a direct-overriding clear, serial input, and serial output pins for cascading. Both the shift register and the storage register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the shift register state will always be one clock pulse ahead of the storage register.