HI5805 Description
It is designed for high speed, high resolution applications where wide bandwidth and low power consumption are essential. The HI5805 is designed in a fully differential pipelined architecture with a front end differential-in-differential-out sample-and-hold (S/H). The HI5805 has excellent dynamic performance while consuming 300mW power at 5MSPS.
HI5805 Key Features
- Sampling Rate
- Low Power
- Internal Sample and Hold
- Fully Differential Architecture
- Full Power Input Bandwidth
- 100MHz
- Low Distortion
- Internal Voltage Reference
- TTL/CMOS patible Digital I/O
- Digital Outputs