HSP50210 - Digital Costas Loop

Datasheet Summary

Description

NAME

Features

Clock Rates Up to 52MHz.
Selectable Matched Filtering with Root Raised Cosine or Integrate and Dump Filter.
Second Order Carrier and Symbol Tracking Loop Filters.
Automatic Gain Control (AGC).
Discriminator for FM/FSK Detection and Discriminator Aided Acquisition.
Swept Acquisition with Programmable Limits.
Lock Detector.
Data Quality and Signal Level Measurements.
Cartesian-to-Polar Converter.
8-Bit Micro.

Renesas

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Datasheet Details

Part number	HSP50210
Manufacturer	Renesas
File Size	2.17 MB
Description	Digital Costas Loop
Datasheet	HSP50210 Datasheet
Additional preview pages of the HSP50210 datasheet.

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HSP50210 Digital Costas Loop OBSOLETE PRODUCT NO RECOMMENDED REPLACEMENT contact our Technical Support Center at www.intersil.com/tsc DATASHEET FN3652 Rev.5.00 Jul 2, 2008 Digital Costas Loop The Digital Costas Loop (DCL) performs many of the baseband processing tasks required for the demodulation of BPSK, QPSK, 8-PSK, OQPSK, FSK, AM and FM waveforms. These tasks include matched filtering, carrier tracking, symbol synchronization, AGC, and soft decision slicing. The DCL is designed for use with the HSP50110 Digital Quadrature Tuner to provide a two chip solution for digital down conversion and demodulation. The DCL processes the In-phase (I) and Quadrature (Q) components of a baseband signal which have been digitized to 10 bits.

Published: Mar 31, 2020 |