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ICS2402 - MULTIPLIER AND ZERO DELAY BUFFER

General Description

The ICS2402 is a high-performance Zero Delay Buffer (ZDB) which integrates IDT’s proprietary analog/digital Phase-Locked Loop (PLL) techniques.

The chip is part of IDT’s ClockBlocksTM family and was designed as a performance upgrade to meet today’s higher speed and lower voltage requirements.

Key Features

  • 8-pin SOIC package.
  • Pb-free, RoHS compliant.
  • Absolute jitter ±100 ps.
  • Propagation Delay of ±600 ps.
  • Output multiplier of 2X.
  • Output clock frequency up to 80 MHz.
  • Can recover degraded input clock duty cycle.
  • Output clock duty cycle of 45/55.
  • Full CMOS clock swings with 25 mA drive capability at TTL levels.
  • Advanced, low power CMOS process.
  • Operating voltage of 3.3 V or 5 V Block Diagram ICLK S0 F.

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Datasheet Details

Part number ICS2402
Manufacturer Renesas
File Size 309.84 KB
Description MULTIPLIER AND ZERO DELAY BUFFER
Datasheet download datasheet ICS2402 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MULTIPLIER AND ZERO DELAY BUFFER DATASHEET ICS2402 Description The ICS2402 is a high-performance Zero Delay Buffer (ZDB) which integrates IDT’s proprietary analog/digital Phase-Locked Loop (PLL) techniques. The chip is part of IDT’s ClockBlocksTM family and was designed as a performance upgrade to meet today’s higher speed and lower voltage requirements. The zero delay feature means that the rising edge of the input clock aligns with the rising edges of both output clocks, giving the appearance of no delay through the device. The ICS2402 is ideal for synchronizing outputs in a large variety of systems, from personal computers to data communications to graphics/video. By allowing off-chip feedback paths, the device can eliminate the delay through other devices.