ICS601-02 Datasheet PDF - Renesas LOW PHASE NOISE CLOCK MULTIPLIER Specs

ICS601-02 - LOW PHASE NOISE CLOCK MULTIPLIER

Datasheet Summary

Description

The ICS601-02 is a low cost, low phase noise, high performance clock synthesizer for any application that requires low phase noise and low jitter.

The ICS601 is IDT’s lowest phase noise multiplier.

Features

Packaged in 16-pin SOIC (Pb free).
Uses fundamental 10 - 27 MHz crystal or clock.
Patented PLL with the lowest phase noise.
Output clocks up to 170 MHz at 3.3 V.
Output Enable function tri-states outptus.
Low phase noise: -132 dBc/Hz at 10 kHz.
Low jitter - 18 ps one sigma.
Full swing CMOS outputs with 25 mA drive capability at TTL levels.
Advanced, low power, sub-micron CMOS process.
Industrial temperatur.

Datasheet Details

Part number	ICS601-02
Manufacturer	Renesas
File Size	322.02 KB
Description	LOW PHASE NOISE CLOCK MULTIPLIER
Datasheet	ICS601-02 Datasheet
Additional preview pages of the ICS601-02 datasheet.

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Full PDF Text Transcription

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LOW PHASE NOISE CLOCK MULTIPLIER DATASHEET ICS601-02 Description The ICS601-02 is a low cost, low phase noise, high performance clock synthesizer for any application that requires low phase noise and low jitter. The ICS601 is IDT’s lowest phase noise multiplier. Using IDT’s patented analog and digital Phase Locked Loop (PLL) techniques, the chip accepts a 10–27 MHz crystal or clock input, and produces output clocks up to 170 MHz at 3.3 V. A separate supply pin is provided so that the output can be 2.5 V. This product is intended for clock generation. It has low output jitter (variation in the output period), but input to output skew and jitter are not defined nor guaranteed. For applications which require defined input to output timing, use the ICS670-01.

Published: May 8, 2020 |