ICS601-21 Datasheet PDF - Renesas LOW PHASE NOISE CLOCK MULTIPLIER Specs

ICS601-21 - LOW PHASE NOISE CLOCK MULTIPLIER

Datasheet Summary

Description

The ICS601-21 is a low-cost, low phase noise, high performance clock synthesizer for applications which require low phase noise and low jitter.

It is IDT’s lowest phase noise multiplier.

Features

Fully integrated PLL, no external loop filter required.
Differential 3.3 V LVPECL outputs.
Uses fundamental crystal or clock.
Crystal input frequency: 10 to 27MHz.
Clock input: 10 to 38MHz (mulitply by 6) 10 to 31MHz (all other multiply settings).
Output clocks up to 230 MHz at 3.3 V.
Low phase noise: -122 dBc/Hz at 10 kHz.
Low jitter - 15 ps one sigma typ.
Powerdown mode lowers power consumption.
Package.

Datasheet Details

Part number	ICS601-21
Manufacturer	Renesas
File Size	268.35 KB
Description	LOW PHASE NOISE CLOCK MULTIPLIER
Datasheet	ICS601-21 Datasheet
Additional preview pages of the ICS601-21 datasheet.

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Full PDF Text Transcription

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LOW PHASE NOISE CLOCK MULTIPLIER DATASHEET ICS601-21 Description The ICS601-21 is a low-cost, low phase noise, high performance clock synthesizer for applications which require low phase noise and low jitter. It is IDT’s lowest phase noise multiplier. Using IDT’s patented analog and digital Phase Locked Loop (PLL) techniques, the chip accepts a crystal or clock input, and produces output clocks up to 230 MHz at 3.3 V. This product is intended for clock generation. It has low output jitter (variation in the output period), but input to output skew and jitter are not defined nor guaranteed. Features • Fully integrated PLL, no external loop filter required • Differential 3.

Published: Sep 26, 2023 |