Datasheet4U Logo Datasheet4U.com

ICS601-21 - LOW PHASE NOISE CLOCK MULTIPLIER

General Description

The ICS601-21 is a low-cost, low phase noise, high performance clock synthesizer for applications which require low phase noise and low jitter.

It is IDT’s lowest phase noise multiplier.

Key Features

  • Fully integrated PLL, no external loop filter required.
  • Differential 3.3 V LVPECL outputs.
  • Uses fundamental crystal or clock.
  • Crystal input frequency: 10 to 27MHz.
  • Clock input: 10 to 38MHz (mulitply by 6) 10 to 31MHz (all other multiply settings).
  • Output clocks up to 230 MHz at 3.3 V.
  • Low phase noise: -122 dBc/Hz at 10 kHz.
  • Low jitter - 15 ps one sigma typ.
  • Powerdown mode lowers power consumption.
  • Package.

📥 Download Datasheet

Datasheet Details

Part number ICS601-21
Manufacturer Renesas
File Size 268.35 KB
Description LOW PHASE NOISE CLOCK MULTIPLIER
Datasheet download datasheet ICS601-21 Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
ICS650-01B System Peripheral Clock Source Integrated Circuit Systems
ICS650-05 HDTV Clock Synthesizer Integrated Circuit Systems
ICS650-07B Broadcom Clock Source Integrated Circuit Systems
ICS650-07C Networking Clock Source Integrated Circuit Systems
ICS650-11 NETWORKING CLOCK SYNTHESIZER IDT

Other Datasheets by Renesas

Part Number Description
ICS601-01 LOW PHASE NOISE CLOCK MULTIPLIER
ICS601-02 LOW PHASE NOISE CLOCK MULTIPLIER
ICS621 LOW SKEW 1 TO 4 CLOCK BUFFER
ICS650-01 SYSTEM PERIPHERAL CLOCK SOURCE
ICS650-07C NETWORKING CLOCK SOURCE

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
LOW PHASE NOISE CLOCK MULTIPLIER DATASHEET ICS601-21 Description The ICS601-21 is a low-cost, low phase noise, high performance clock synthesizer for applications which require low phase noise and low jitter. It is IDT’s lowest phase noise multiplier. Using IDT’s patented analog and digital Phase Locked Loop (PLL) techniques, the chip accepts a crystal or clock input, and produces output clocks up to 230 MHz at 3.3 V. This product is intended for clock generation. It has low output jitter (variation in the output period), but input to output skew and jitter are not defined nor guaranteed. Features • Fully integrated PLL, no external loop filter required • Differential 3.