ICS663 Overview
The ICS663 is a low cost Phase-Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled Oscillator (VCO) and an output buffer. Through the use of external reference and VCO dividers (implemented with the ICS674-01, for example), the user can easily configure the device to lock to a wide variety of input frequencies.
ICS663 Key Features
- Packaged in 8-pin SOIC (Pb free)
- External PLL loop filter enables configuration for a wide
- Ability to accept an input clock in the kHz range (video
- 25 mA output drive capability at TTL levels
- Lower power CMOS process
- +3.3 V ±5% or +5 V ±10% operating voltage
- Used along with the ICS674-01, forms a plete PLL
- Phase detector and VCO blocks can be used
- Industrial temperature version available
- For better jitter performance, use the MK1575
ICS663 Applications
- Packaged in 8-pin SOIC (Pb free)
- Output clock range 1 MHz to 100 MHz (3.3 V), 1 MHz to
- External PLL loop filter enables configuration for a wide
- Ability to accept an input clock in the kHz range (video