ICS663 - PLL BUILDING BLOCK

Product Overview

Renesas

Part number	ICS663
Manufacturer	Renesas
File Size	352.97 KB
Description	PLL BUILDING BLOCK
Datasheet	ICS663 Datasheet
Additional preview pages of the ICS663 datasheet.

The ICS663 is a low cost Phase-Locked Loop (PLL) designed for clock synthesis and synchronization.

Included on the chip are the phase detector, charge pump, Voltage Controlled Oscillator (VCO) and an output buffer.

please refer to the ICS673-01. Features.
Packaged in 8-pin SOIC (Pb free).
Output clock range 1 MHz to 100 MHz (3.3 V), 1 MHz to 120 MHz (5 V).
External PLL loop filter enables configuration for a wide range of input frequencies.
Ability to accept an input clock in the kHz range (video Hsync, for example).
25 mA output drive capability at TTL levels.
Lower power CMOS process.
+3.3 V ±5% or +5 V ±10% operating voltage.
Used.

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Published: Jun 4, 2020 |