ICS670-01 Datasheet | Renesas

LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER Description The ICS670-01 is a high-speed, low phase noise, Zero Delay Buffer (ZDB) which integrates IDT’s proprietary analog/digital Phase Locked Loop (PLL) techniques. The zero delay feature means that the rising edge of the input clock aligns with the rising edges of the outputs. There are two identical outputs on the chip. FBCLK should be connected to FBIN. Each output has its own output enable pin. The ICS670-01 is ideal for synchronizing outputs in a large variety of systems, from personal puters to data munications to video. By allowing off-chip feedback paths, the ICS670-01 can eliminate the delay through other devices. The 15 different on-chip multipliers work in a variety of applications. Arbitrary multiplication factors (including fractions) can be configured on the ICS527. Block Diagram Features - Packaged in 16-pin SOIC - Pb (lead) free package, Ro HS pliant - Clock inputs from 5 to 160 MHz (see page 2) - Patented PLL with low phase noise - Output clocks up to 160 MHz at 3.3 V - 15 selectable on-chip multipliers - Power down mode available - Low phase noise: -124 d Bc/Hz at 10 k Hz - Output enable function tri-states outputs - Low jitter- 15 ps one sigma - Full swing CMOS outputs with 25 m A drive capability at TTL levels - Advanced, low power, sub-micron CMOS process - Industrial temperature version available - Operating voltage of 3.3 V or 5 V ICLK FBIN Phase Detector, Charge Pump, and Loop Filter Voltage Controlled Oscillator OE1 ROMBased Multipliers FBCLK S3:S0 GND External Feedback from FBCLK is...