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ICS854104 Datasheet Differential-to-lvds Fanout Buffer

Manufacturer: Renesas

Overview: Low Skew, 1-to-4, Differential-to-LVDS Fanout Buffer ICS854104 DATASHEET.

Datasheet Details

Part number ICS854104
Manufacturer Renesas
File Size 713.74 KB
Description Differential-to-LVDS Fanout Buffer
Datasheet ICS854104-Renesas.pdf

General Description

The ICS854104 is a low skew, high performance 1-to-4 Differential-to-LVDS Clock Fanout Buffer.

Utilizing Low Voltage Differential Signaling (LVDS), the ICS854104 provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100.

The ICS854104 accepts a differential input level and translates it to LVDS output levels.

Key Features

  • Four differential LVDS output pairs.
  • One differential clock input pair.
  • CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL.
  • Each output has an individual OE control.
  • Maximum output frequency: 700MHz.
  • Translates differential input signals to LVDS levels.
  • Additive phase jitter, RMS: 0.232ps (typical).
  • Output skew: 50ps (maximum).
  • Part-to-part skew: 350ps (maximum).

More Datasheets from Renesas

Part Number Description
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ICS854S01I 2:1 Differential-to-LVDS Multiplexer
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ICS854S296I-33 LVDS Programmable Delay-Line
ICS854S54I-01 Differential-to-LVDS Multiplexer

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