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ICS9173B - VIDEO GENLOCK PLL

General Description

The ICS9173B provide the analog PLL circuit blocks to implement a frequency multiplier.

Because the device is configured to use an external divider in the PLL clock feedback path, a large divider can be used to result in a large frequency multiplication ratio.

Key Features

  • Phase-detector/VCO circuit block.
  • Ideal for genlock system.
  • Reference clock range 12 kHz to 1 MHz for full output clock range.
  • Output clock range of 1.25 to 75 MHz (-01), and 0.625 to 37.5 MHz (-15). See “Allowable Input Frequency to Output Frequency” table for conditions.
  • On-chip loop filter.
  • Single 5 V power supply.
  • Low power CMOS technology.
  • 8-pin SOIC package Block Diagram IDT® VIDEO.

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Datasheet Details

Part number ICS9173B
Manufacturer Renesas
File Size 327.75 KB
Description VIDEO GENLOCK PLL
Datasheet download datasheet ICS9173B Datasheet

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Full PDF Text Transcription (Reference)

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VIDEO GENLOCK PLL DATASHEET ICS9173B Description The ICS9173B provide the analog PLL circuit blocks to implement a frequency multiplier. Because the device is configured to use an external divider in the PLL clock feedback path, a large divider can be used to result in a large frequency multiplication ratio. This is useful when using a low frequency input clock to generate a high frequency output clock. The ICS9173B contains a phase detector, charge pump, loop filter, and voltage-controlled oscillator (VCO). The ICS674-01 can be used as the external feedback divider. A common application of the ICS9173B is the implementation of a video genlock circuit. Because of this, the ICS9173B inputs operate on the negative-going clock edge.