ICS9FG1201H Datasheet | Renesas

Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD Description The ICS9FG1201H follows the Intel DB1200G Rev 1.0 Differential Buffer Specification. This buffer provides 12 output clocks for CPU Host Bus, PCI-Express, or Fully Buffered DIMM applications. The outputs are configured with two groups. Both groups (DIF 9:0) and (DIF 11:10) can be equal to or have a gear ratio to the input clock. A differential CPU clock from a CK410B or CK410B+ main clock generator, such as the ICS932S421, drives the ICS9FG1201. The ICS9FG1201H can provide outputs up to 400MHz Key Specifications - DIF output cycle-to-cycle jitter < 50ps - DIF output-to-output skew < 50ps within a...