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ICSSSTVA16859C - DDR 13-Bit to 26-Bit Registered Buffer

General Description

The 13-bit-to-26-bit ICSSSTVA16859C is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/O levels, except for the LVCMOS RESET# input.

Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#).

Key Features

  • Differential clock signals.
  • Meets SSTL_2 signal data.
  • Supports SSTL_2 class I specifications on outputs.
  • Low-voltage operation - VDD = 2.3V to 2.7V.
  • Available in 64 pin TSSOP and 56 pin MLF packages.
  • Exceeds ICSSSTVN16859 performance Truth Table1 RESET# L H H H Notes: Inputs CLK CLK# X or X or Floating Floating ↑↓ ↑↓ L or H L or H Q Outputs DQ X or Floating L HH LL X Q0(2) 1. H = "High" Signal Level L = "Low" Signal Level ↑.

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Datasheet Details

Part number ICSSSTVA16859C
Manufacturer Renesas
File Size 495.39 KB
Description DDR 13-Bit to 26-Bit Registered Buffer
Datasheet download datasheet ICSSSTVA16859C Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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ICSSSTVA16859C DDR 13-Bit to 26-Bit Registered Buffer Recommended Applications: • DDR Memory Modules: - DDRI (PC1600, PC2100) - DDR333 (PC2700) - DDRI-400 (PC3200) • Provides complete DDR DIMM solution with ICS93V857 or ICS95V857 • SSTL_2 compatible data registers Product Features: • Differential clock signals • Meets SSTL_2 signal data • Supports SSTL_2 class I specifications on outputs • Low-voltage operation - VDD = 2.3V to 2.7V • Available in 64 pin TSSOP and 56 pin MLF packages • Exceeds ICSSSTVN16859 performance Truth Table1 RESET# L H H H Notes: Inputs CLK CLK# X or X or Floating Floating ↑↓ ↑↓ L or H L or H Q Outputs DQ X or Floating L HH LL X Q0(2) 1.