• Part: IDT7210
  • Description: 16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
  • Manufacturer: Renesas
  • Size: 306.67 KB
Download IDT7210 Datasheet PDF
Renesas
IDT7210
IDT7210 is 16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR manufactured by Renesas.
- Part of the IDT7210L comparator family.
16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR IDT7210L Integrated Device Technology, Inc. Features : - 16 x 16 parallel multiplier-accumulator with selectable accumulation and subtraction - High-speed: 20ns multiply-accumulate time - IDT7210 Features selectable accumulation, subtraction, rounding and preloading with 35-bit result - IDT7210 is pin and function patible with the TRW TDC1010J, TMC2210, Cypress CY7C510, and AMD AM29510 - Performs subtraction and double precision addition and multiplication - Produced using advanced CMOS high-performance technology - TTL-patible - Available in topbraze DIP, PLCC, Flatpack and Pin Grid Array - Military product pliant to MIL-STD-883, Class B - Standard Military Drawing #5962-88733 is listed on this function - Speeds available: mercial: L20/25/35/45/55/65 Military: L25/30/40/55/65/75 DESCRIPTION: The IDT7210 is a high-speed, low-power 16 x 16-bit parallel multiplier-accumulator that is ideally suited for real-time digital signal processing applications. Fabricated using CMOS silicon gate technology, this device offers a very low-power alternative to existing bipolar and NMOS counterparts, with only 1/7 to 1/10 the power dissipation and exceptional speed (25ns maximum) performance. A pin and functional replacement for TRW’s TDC1010J the IDT7210 operates from a single 5 volt supply and is patible with standard TTL logic levels. The architecture of the IDT7210 is fairly straightforward, featuring individual input and output registers with clocked D-type flip-flop, a preload capability which enables input data to be preloaded into the output registers, individual three-state output ports for the Extended Product (XTP) and Most Significant Product (MSP) and a Least Significant Product output (LSP) which is multiplexed with the Y input. The XIN and YIN data input registers may be specified through the use of the Two’s plement input (TC) as either a two’s plement or an unsigned magnitude, yielding a...