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IDT74ALVCH16260 - 12-bit to 24-bit multiplexed D-type latch

General Description

This 12-bit to 24-bit multiplexed D-type latch is built using advanced dual metal CMOS technology.

The ALVCH16260 is used in applications in which two separate data paths must be multiplexed onto, or demultiplexed from, a single data path.

Key Features

  • 0.5 MICRON CMOS Technology.
  • Typical tSK(o) (Output Skew) < 250ps.
  • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0).
  • VCC = 3.3V ± 0.3V, Normal Range.
  • VCC = 2.7V to 3.6V, Extended Range.
  • VCC = 2.5V ± 0.2V.
  • CMOS power levels (0.4μ W typ. static).
  • Rail-to-Rail output swing for increased noise margin.
  • Available in TSSOP package DRIVE.

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Datasheet Details

Part number IDT74ALVCH16260
Manufacturer Renesas
File Size 209.26 KB
Description 12-bit to 24-bit multiplexed D-type latch
Datasheet download datasheet IDT74ALVCH16260 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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IDT74ALVCH16260 3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS AND BUS-HOLD IDT74ALVCH16260 FEATURES: • 0.5 MICRON CMOS Technology • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • VCC = 2.5V ± 0.2V • CMOS power levels (0.4μ W typ. static) • Rail-to-Rail output swing for increased noise margin • Available in TSSOP package DRIVE FEATURES: • High Output Drivers: ±24mA • Suitable for heavy loads APPLICATIONS: • 3.3V high speed systems • 3.