KAD5514P Datasheet | Renesas

Features - Programmable gain, offset, and skew control - 950MHz analog input bandwidth - 60fs clock jitter - Over-range indicator - Selectable clock divider: ÷1, ÷2, or ÷4 - Clock phase selection - Nap and sleep modes - Two’s plement, gray code or binary data format - DDR LVDS-patible or LVCMOS outputs - Programmable built-in test patterns - Single-supply 1.8V operation - Pb-free (Ro HS pliant) Key Specifications - SNR = 69.4d BFS for f IN = 105MHz (-1d BFS) - SFDR = 82.2d Bc for f IN = 105MHz (-1d BFS) - Total power consumption ○ 429/345m W at 250/125MSPS (SDR Mode) ○ 390/309m W at 250/125MSPS (DDR Mode) Related Literature For a full list of related documents, visit our website: - KAD5514P-12, KAD5514P-17, KAD5514P-21, KAD5514P-25 device pages AVDD CLKDIV OVDD FN6804 Rev.4.00 Jun.17.19 CLKP CLKN VINP VINN VCM Clock Generation 1.25V + - 14-Bit 250 MSPS SPI Control Digital Error Correction LVDS/CMOS Drivers CLKOUTP CLKOUTN D[13:0]P D[13:0]N ORP ORN OUTFMT OUTMODE NAPSLP AVSS CSB SCLK SDIO SDO OVSS Figure 1. Block...