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M6MGT321S4TP - CMOS SRAM

Description

M6MGB/T321S4TP provides for Software Lock Release function.

Usually, all memory blocks are locked and can not be programmed or erased, when F-WP# is low.

Using Software Lock Release function, program or erase operation 32M-bit Flash memory is a 4,194,304 bytes / 2,097,152 words, can be executed.

Features

  • DINOR (Divided bit-line NOR) architecture for the memory cell. Access Time Flash 85ns (Max. ) 4M-bit SRAM is a 524,288 bytes / 262,144 words SRAM 85ns (Max. ) asynchronous SRAM fabricated by silicon-gate CMOS technology. Supply Voltage VCC=2.7 ~ 3.6V The M6MGB/T321S4TP is a Stacked micro Multi Chip Package (S- µMCP) that contents 32M-bit Flash memory and 4M-bit Static RAM in a 52-pin TSOP. M6MGB/T321S4TP is suitable for the.

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Datasheet Details

Part number M6MGT321S4TP
Manufacturer Renesas
File Size 92.80 KB
Description CMOS SRAM
Datasheet download datasheet M6MGT321S4TP Datasheet
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Full PDF Text Transcription

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www.DataSheet4U.com Renesas LSIs M6MGB/T321S4TP 33,554,432-BIT (2,097,152 - WORD BY 16-BIT/4,194,304-WORD BY 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY & 4,194,304-BIT (262,144-WORD BY 16-BIT/524,288-WORD BY 8-BIT) CMOS SRAM Stacked - µ MCP (micro Multi Chip Package) Description M6MGB/T321S4TP provides for Software Lock Release function. Usually, all memory blocks are locked and can not be programmed or erased, when F-WP# is low. Using Software Lock Release function, program or erase operation 32M-bit Flash memory is a 4,194,304 bytes / 2,097,152 words, can be executed. 3.3V-only, and high performance non-volatile memory fabricated by CMOS technology for the peripheral circuit and Features DINOR (Divided bit-line NOR) architecture for the memory cell. Access Time Flash 85ns (Max.
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