MPC9446 Datasheet | Renesas

Features - Configurable 10 outputs LVCMOS clock distribution buffer - patible to single, dual and mixed 3.3 V/2.5 V voltage supply - Wide range output clock frequency up to 250 MHz - Designed for mid-range to high-performance tele, networking and puter applications - Supports applications requiring clock redundancy - Maximum output skew of 200 ps (150 ps within one bank) - Selectable output configurations per output bank - Tristable outputs - 32-lead LQFP package, Pb-free - Ambient operating temperature range of - 40 to 85C - For drop in replacement part use 87946AYI-147 LOW VOLTAGE SINGLE OR DUAL SUPPLY 2.5 V AND 3.3 V LVCMOS CLOCK DISTRIBUTION BUFFER AC SUFFIX 32-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 873A-04 Functional Description The MPC9446 is a full static fanout buffer design supporting clock frequencies up to 250 MHz. The signals are generated and retimed on-chip to ensure minimal skew between the three output banks. Two independent LVCMOS patible clock inputs are available. This feature supports redundant clock sources or the addition of a test clock into the system design. Each of the three output banks can be individually supplied by 2.5 V or 3.3 V supporting mixed voltage applications. The FSELx pins choose between division of the input reference frequency by one or two. The frequency divider can be set individually for each of the three output banks. The MPC9446 can be reset and the outputs are disabled by deasserting the MR/OE pin (logic high state). Asserting MR/ OE will enable the outputs. All inputs accept LVCMOS signals while the outputs provide LVCMOS patible levels with the capability to drive terminated 50  transmission lines. Please consult the MPC9456 specification for a 1:10 mixed voltage buffer with LVPECL patible inputs. For series terminated transmission lines, each of the MPC9446 outputs can drive one or two traces giving the devices an effective fanout of 1:20. The device is packaged in a 7x7 mm2 32-lead LQFP...