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MPC962305 - 3.3V Zero Delay Buffer

General Description

1.

Weak pull-down.

2.

Key Features

  • 1:5 LVCMOS zero-delay buffer (MPC962305).
  • 1:9 LVCMOS zero-delay buffer (MPC962309).
  • Zero input-output propagation delay.
  • Multiple low-skew outputs.
  • 250 ps max output-output skew.
  • 700 ps max device-device skew.
  • Supports a clock I/O frequency range of 10 MHz to 133 MHz, compatible with CPU and PCI bus frequencies.
  • Low jitter, 200 ps max cycle-cycle, and compatible with Pentium® based systems.
  • Test Mode to bypass PLL.

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Datasheet Details

Part number MPC962305
Manufacturer Renesas
File Size 765.15 KB
Description 3.3V Zero Delay Buffer
Datasheet download datasheet MPC962305 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Low-Cost, 3.3V Zero Delay Buffer MPC962305 PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016 DATASHEET The MPC962309 is a zero delay buffer designed to distribute high-speed clocks. Available in a 16-pin SOIC or TSSOP package, the device accepts one reference input and drives nine low-skew clocks. The MPC962305 is the 8-pin version of the MPC962309 which drives five outputs with one reference input. The -1H versions of these devices have higher drive than the -1 devices and can operate up to 100/-133 MHz frequencies. These parts have on-chip PLLs which lock to an input clock presented on the REF pin. The PLL feedback is on-chip and is obtained from the CLOCKOUT pad.